1. Field of the Invention
The present invention relates to a model parameter extracting apparatus and a model parameter extracting program for a semiconductor device model.
2. Description of the Related Art
A circuit simulation using a circuit simulator is carried out when LSI circuits are designed. In the circuit simulation, a semiconductor device model is assigned a model parameter (a device parameter) thereby to show the characteristic of the semiconductor device. Thereby, the operation of the circuit is calculated in a simulated manner. The accuracy and reliability of the circuit simulation is determined by the setting of the model parameter assigned to the semiconductor device model.
Many device model parameters are provided for device models such as Berkeley short-channel insulated gate field effect transistor (IGFET) model (BSIM). The values of these device model parameters need be adjusted in advance so as to minimize the error between an actual current-voltage characteristic of a transistor and a current-voltage characteristic calculated by a circuit simulation. Work for this adjustment is termed as “parameter extraction” or “tuning.”
A technology of extracting a model parameter accurately representing the characteristic of a semiconductor device is known (see, for instance, Japanese Patent Application Publication No. 2001-119017 (referred to as Patent Document 1 below)). Patent Document 1 discloses a binning technology in which the area of a device having a gate length L and a gate width W is divided by a lattice into sub-areas termed as “bins” (containers).
A binning technology disclosed in Patent Document 1 is implemented as follows. First, for each of MOSFETs having different gate lengths, a direct current-DC voltage characteristic is measured, and a threshold voltage is calculated from the direct current-DC voltage characteristic thus obtained. Then, for each MOSFET, a channel resistance is measured. Thereafter, an Rd-L characteristic representing a relationship between the channel resistance and the gate length is calculated from the calculated threshold voltage and the measured value of the channel resistance. Then, a linear approximation is applied to the Rd-L characteristics of the respective MOSFETs with respect to the gate length. When a straight line is obtained for a model parameter for each effective gate bias voltage, a global straight line gradient value calculator 31 calculates a gradient value of a global straight line which is obtained by applying the linear approximation to the Rd-L characteristic with respect to all the gate lengths. Subsequently, a local straight line gradient value calculator 32 calculates a gradient value of each local straight line between adjacent measurement points of the channel resistance. Thereafter, a gradient value crossover point detector 33 finds a crossover point between the adjacent gradient value of the local straight line, and the gradient value of the global straight line, and thereby detects the gate length corresponding to this crossover point, as a gate length in which the measurement value of the channel resistance deviates from the model parameter.
The binning technology reproduces the current-voltage characteristic with accuracy as follows. For each bin, a model parameter is extracted from data on the current-voltage characteristic of an area of the bin. Thereby, all the bins are provided with their respective model parameters. When a circuit simulation is carried out, these multiple model parameters are properly applied to right areas with the gate lengths L corresponding to the bins, respectively.
In general, whether or not each extracted model parameter is suitable is verified by use of a circuit simulator. The circuit simulator can show an electric characteristic of a semiconductor device on the basis of the extracted model parameter. Whether or not the extracted model parameter is suitable is verified on the basis of whether or not an electric characteristic reproduced by the circuit simulator accurately represents the actual electric characteristic of the semiconductor device.
FIGS. 1A and 1B are diagrams showing a result of verification using a conventional circuit simulator. FIG. 1B is a diagram showing a reproduced electric characteristic of a semiconductor device model for an area 21 shown in FIG. 1A. Conventionally, when some part of the reproduced electric characteristic of the semiconductor device model is found to deviate from an expected characteristic (hereinafter the deviating part will be referred to as “deflection of the model trait”), a model parameter is extracted again.
In the conventional technology, a model parameter is repeatedly extracted until the extracted model parameter accurately reproduces the actual characteristic of the semiconductor device. For this reason, the extracted model parameter can reproduce the current-voltage characteristic of the semiconductor device accurately. However, the verification using the circuit simulator for the extraction is complicated and very time consuming. Furthermore, whether or not a more suitable model parameter, which eliminates deflection of the model trait, can be extracted after the verification using the circuit simulator depends on the skill level of a person in charge of the extraction.